====== Kintex Ultrascale KU060 Dynamic Tests ======
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===== NOTES =====
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  * do not use an ion mask to cover parts of the chip from radiation
    * otherwise adds uncertainty and can cause inflated upset rates due to upsets in routing resources
    * suggestion from Alex Harding
  * SEAKR tested MMCM and PLLs
    * worth looking at "unique" features, maybe cascading 
  * Alex and Eliot would like to have a FF test case and microblaze/larger design behavior
    * push luts between FFs and compare results to FF to determine LUT rate?
  * otherwise just build up based on utilization of core test designs (CMTs, BRAM, LUTS, IOBs)
  * From Xilinx there is a desire for a second point/2nd oppinion of view/reference perspective/re-confirmation on the tests done by Melanie

===== TODO =====
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  * <del>Check what IP and which designs can be reused from older boards (see other wiki pages)</del>
  * Develop test designs for below listed test cases, as well as:
    * MGT performance and signal integrity (as this was a major point during schematic and stackup design)
    * FMC daughter card testing
    * FMC commercial card support (as this was a major point during schematic and stackup design)
    * any other new, relevant ultrascale feature (add something!)


===== Acceptance Tests =====

This designs verifies basic board connectivity of a DuT Card. The test design consists of two independent parts: 
  * a software-based pin-connectivity for HD/HR pins on all interfaces and connectors (3x TeraDyne, 2x FMC, dedicated SMA and pin-header accessible IO)
  * an IBERT implementation for verifying MGT connectivity and signal integrity.

===== Test Designs =====

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==== MMCM/PLL tests ====
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DUT design: (Reuse of the V7)\\
  * integrate comment from V7 testing: 
    * move clock source IOBs back to different banks.
  * Status:
    * ported project to KU060 and synthesizes OK, checked with to Michael Eller
    * constraints updated and logic as well as TMR are still workable on ultrascale
    * place & route currently fails, discussed with Bryce on 2021-01-18's call
      * Hypothesis: requires manual IBUFG_CE placement and some additional contraints to constrain the clock path routing

Funcmon design: (Reuse of the V7)\\
  * Stimulus/Frontend part:
    * Status
      * need constraints update
      * needs checking if it works/synthesizes on ku060
  * Datalogger/Backend part:
    * planned to be replaced with an ethernet logger

Currently assigned to: Bryce Hodson @ Boeing
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==== IOB LVCMOS (1V8) std. tests ====
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DUT design: (Reuse of the V7)\\
  * Changes:
    * None to the design itself as it works nicely
    * However, we will focus on this IOB mode to collect more data on it, in favor of spreading to different IOB modes
  * Status:
    * Phil is currently finishing updating constraints
    * otherwise the DUT-side of the design works

Funcmon design: (Reuse of the V7)\\
  * Stimulus/Frontend part:
    * Status
      * work on porting funcmon is in progress
  * Datalogger/Backend part:
    * planned to be replaced with an ethernet logger

Currently assigned to: Phil Park @ Boeing
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==== IOB LVDS std. tests ====
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DUT design: (Reuse of the V7)
  * update constraints

Funcmon design: (Port forward of the V2 design)\\
  * Stimulus/Frontend part:
    * update constraints
    * needs checking if it works/synthesizes on ku060
  * Datalogger/Backend part:
    * planned to be replaced with an ethernet logger

Currently assigned to: Phil Park @ Boeing
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==== IOB MaxIO (LVCMOS 1V8 & LVDS stds.) tests ====
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Currently there are no plans to port this design forward. We plan to test pure LVDS and LVCMOS designs. Feel free to contribute a design.

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==== SERDES (ISERDES/OSERDES) tests ====
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Currently there are no plans to port this design forward. We plan to test pure LVDS and LVCMOS designs. Feel free to contribute a design.

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==== IOB HSTL std. tests ====
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V7 test IP is proprietary, and its source is unavailable to the XRTC. Feel free to contribute a design.

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==== BRAM/BRAM-ECC tests ====
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As of Mid 2020, V7 BRAM test design is not available to the XRTC in source, so can not be ported forward. Instead, test setup would have to be re-developed based on the old V5 BRAMX designs, where we have source. Feel free to contribute a design.

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==== DSP tests ====
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DUT design: (Reuse of the V5)
  * MUL & counter
    * seems to synthesize, needs minor rework to accommodate architecture changes between v7 and US
  * need to update constraints
  * needs checking if it actually works on ku060

Funcmon design: (Reuse of the V7)\\
  * update constraints
  * needs checking if it actually works on ku060

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==== FF tests ====

Discovered while checking Michael Eller's test IP set with CF.\\
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DUT design: (Reuse of the V5)
  * no changes made, old project is from ISE10, seems to synthesize for US
  * need to update constraints
  * needs checking if it actually works on ku060

Funcmon design: (Reuse of the V7)\\
  * no changes made, old project is from ISE10, unknown status
  * update constraints
  * needs checking if it actually works on ku060